Conventional technologies for manufacturing trench semiconductor power devices are continuously challenged to further reduce the manufacturing cost by reducing the number of masks applied in the manufacturing process. For example, for a trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) integrated with Zener diodes for ESD (Electronic Static Discharge) protection and for avalanche capability improvement, simplifying the manufacturing process and cutting down the manufacturing cost without degrading performance is mainly required by device designing and manufacturing.
In U.S. Pat. No. 8,004,009 which has same inventor name and assignee name as the present patent application, a trench MOSFET with Zener diodes for providing ESD protection is disclosed, please refer to FIG. 1A and FIG. 1B for side cross-sectional views showing some of the process steps to make the same. In FIG. 1A, a photo resist 101 is employed as a source mask followed by an Arsenic or Phosphorus ion implantation to form n+ source regions 102 for an N-channel trench MOSFET and n+ doped regions 103 for the Zener diodes which is padded by a thick insulation layer 107 overlying a Nitride layer 108 formed onto a thin oxide layer 110. In FIG. 1B, after removing away the source mask, a contact interlayer 104 is deposited covering a top surface of the thin oxide layer 110, an outer surface of a structure composed of the Zener diodes, the thick insulation layer 107 and the Nitride layer 108. Then, onto the contact interlayer 104, a contact mask (not shown) is applied to open a plurality of contact trenches 105 for formation of trenched contacts for the Zener diodes and for the N-channel trench MOSFET. Afterwards, p+ body contact regions 106 are formed wrapping bottoms of the contact trenches 105 underneath n+ source regions 111 in P body regions 112 of the N-channel trench MOSFET.
FIG. 1C is a top view of the N-channel trench MOSFET integrated with the Zener diodes of the prior art discussed above, which shows that a gate metal is deposited crossing over the Zener diodes (underneath the gate metal) to connect to trenched gate contacts, for example formed in the contact trench 105 extending into a trenched gate as shown in FIG. 1B.
The invention of U.S. Pat. No. 8,004,009 has to use both a source mask and a contact mask. The source mask is used to defined source regions of trench MOSFET and n+ regions on the Zener diode while the contact mask is used to define the trenched contacts for the gate metal and a source metal connections. Each of the n+ source region 111 has a same doping concentration from a channel region to an adjacent contact trenches 105 penetrating through the n+ source region 111 at a same distance from a top surface of an N epitaxial layer 120 wherein the prior art is formed, and has a same source junction depth along the top surface of the N epitaxial layer 120 from the channel region to the adjacent contact trench 105. Moreover, the manufacturing process is complicated due to additional nitride deposition and etching processes.
Therefore, there is still a need in the art of the semiconductor power device integrated with a clamp diode, to provide a novel cell structure, device configuration and fabrication process that would further reduce the number of masks applied in the manufacturing process without additional costs and minimize the number of the manufacturing process steps.